Method and apparatus for contemporaneously compiling an electronic circuit design by contemporaneously bipartitioning the electronic circuit design using parallel processing
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United States of America Patent
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Jun 27, 2000
Grant Date -
N/A
app pub date -
Oct 27, 1997
filing date -
Oct 27, 1997
priority date (Note) -
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Abstract
Disclosed are various techniques for deploying multiple processing resources, operating in parallel, to compile electronic designs. The disclosed methods identify 'compilation tasks' that can be performed in isolation from the remainder of a large 'compilation project.' When one of these stand alone compilation tasks is identified, it can be temporarily segregated and performed by one or more processors which are not working on other tasks. Simultaneously, the remainder of the project compiles under one or more other processors. One class of severable compilation projects includes those projects that contain multiple full compilation tasks, each of which involves compiling a single design from start to finish. Another class of divisible compilation projects includes those projects in which the logical hierarchy of an electronic design provides the boundaries between isolated compilation tasks. Yet another class of divisible compilation projects are projects in which the tasks are divided out based upon an architecture of a target hardware device.
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