Dynamic NOR gates for NAND decode
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United States of America Patent
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-
Jun 27, 2000
Grant Date -
N/A
app pub date -
Dec 19, 1997
filing date -
Dec 19, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A NOR gate pair includes a first and second NOR gate, each with a plurality of inputs and an output. A first NAND gate has a first input coupled to the output of the first NOR gate, a second input coupled to the output of the second NOR gate through a first input inverter, and an output. A second NAND gate has a first input coupled to the output of the second NOR gate, a second input coupled to the output of the first NOR gate through a second input inverter, and an output. A first output inverter is coupled to the output of the first NAND gate and a second output inverter is coupled to the output of the second NAND gate. This configuration assures that NOR gates used in a one-hot-decode decoder will all have logic-low outputs during a precharge phase.
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