Merging dummy structure representations for improved distribution of artifacts in a semiconductor layer
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United States of America Patent
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Jun 27, 2000
Grant Date -
N/A
app pub date -
Sep 30, 1997
filing date -
Sep 30, 1997
priority date (Note) -
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Abstract
A method for optimally sizing dummy structures in an integrated circuit design is disclosed. Adjacent dummy structures are merged to provide a composite merged dummy structure. Each side of a first dummy structure representation is expanded in a lateral direction by a predetermined distance such that the first dummy structure representation merges with an adjacent second dummy structure representation forming the composite merged dummy structure. The composite merged dummy structure is then examined to determine if it exceeds a predetermined size. If the composite merged dummy structure exceeds the predetermined size, then the composite merged dummy structure is contracted to fit within predetermined perimeters.
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