FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode
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United States of America Patent
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Jun 27, 2000
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N/A
app pub date -
Dec 15, 1998
filing date -
Dec 15, 1998
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Abstract
A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals, including a read-mode (RMODE) control signal that switches the memory block between synchronous and asynchronous data transfer modes. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.
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