PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
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United States of America Patent
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Jul 4, 2000
Grant Date -
N/A
app pub date -
Apr 24, 1998
filing date -
Apr 24, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A window pane architecture for FPGAs utilizes spaced subarrays having routing channels therebetween. In one embodiment, at least one routing channel includes segmented and staggered routing wires to minimize current loading and capacitive time delay. Connections between the configurable logic blocks, interconnect, and routing wires may be accomplished with switch matrices and programmable interconnect points.
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