Semiconductor memory device
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United States of America Patent
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Jul 4, 2000
Grant Date -
N/A
app pub date -
Apr 16, 1998
filing date -
Apr 16, 1998
priority date (Note) -
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Abstract
A semiconductor memory device includes a memory cell array having memory cells arranged in rows and columns. Bit lines are coupled to the memory cells in corresponding columns and word lines are arranged to be substantially orthogonal to the bit lines, each word line coupled to the memory cells in a corresponding row. The memory cell array is divided into an odd number of sub-arrays which are spaced apart from each other in the word line direction. No bit lines and no memory cells are formed in the spaces between the sub-arrays.
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