System bus arbitrator for facilitating multiple transactions in a computer system
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United States of America Patent
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Jul 4, 2000
Grant Date -
N/A
app pub date -
Apr 13, 1998
filing date -
Apr 13, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
A method and an apparatus using, in one embodiment, a multiple split mode for issuing multiple read or write requests that may be used during a data transaction within a computer system. In one embodiment, a processing unit comprises a bus arbitrator having bus control lines for controlling a bus, which transmits address and data information. The arbitrator is capable of issuing multiple consecutive read or write requests including at least one read request on the bus without releasing control by the processing unit over the bus during the consecutive read or write requests. In addition, the arbitrator is also designed to abort consecutive read requests during address cycles in response to bus control lines.
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