DRAM system with simultaneous burst read and write

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United States of America Patent

PATENT NO 6085300
SERIAL NO

08934034

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Abstract

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A DRAM system is described that can prevent a substantial reduction in bandwidth with respect to a clock pulse frequency even when banks are accessed in no specific order. As a result, provided is a memory system constituted by DRAM whereby a seamless operation is assured not only for reading but also for writing.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sunaga, Toshio Kusatsu, JP 49 483
Watanabe, Shinpei Yokohama, JP 37 466

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