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Abstract

Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has a pre-processing phase during which task graphs, system/task constraints, and a resource library for the embedded system are parsed, wherein the resource library has different PEs requiring different power supply voltages. The algorithm also has a synthesis phase, following the pre-processing phase, during which groups of tasks in the task groups are allocated to the PEs in the resource library and edges in the task graphs are allocated to communicate links in the resource library, based on performance evaluation of one or more possible allocations for each of the groups and edges in light of the system/task constraints, wherein (1) two or more PEs in the embedded system use two or more different power supply voltages (2) power dissipation is considered, along with cost and real-time constraints, during at least one of task grouping, group/edge allocation, and/or performance evaluation.

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First Claim