Semiconductor memory device having a power-down mode
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United States of America Patent
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Jul 11, 2000
Grant Date -
N/A
app pub date -
Aug 11, 1998
filing date -
Aug 13, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
When a clock enable signal asynchronous with a clock signal is set at a high level, a power-down control circuit sets a power-down signal at a high level to release a power-down mode. When the power-down mode is released, a clock control circuit outputs an internal clock signal such that an output signal of a command decoder can be latched. According to such a constitution, a period of time from the latching of the command after releasing the power-down mode to the time when the command can be transferred will be reduced, and a high-speed operation can be attained.
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