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Abstract

The present invention concerns a high resolution calibrator for a sleep mode clock of a mobile station in a wireless communications system. When the mobile station is in idle mode (i.e., listening to a paging channel periodically, but otherwise taking no action), the control processor commands the mobile station to enter into sleep mode to minimize power consumption. During sleep mode, the high-frequency reference clock and circuitry clocked by it are turned off. Only the calibrated low-frequency clock remains operating to clock the sleep logic. In a preferred version, the calibrator includes two counters: a first counter which counts up to S*T0 cycles of the super chip rate clock through one data frame, then rolls over to zero, and a second counter which counts cycles of the sleep mode clock. Also included are three registers: a first register which stores a first value CNTSLP which is input from the second counter at the end of a calibration period and subsequently at wake up time; a second register which stores a second value SYSTIME1 which is input from the first counter at the beginning of a calibration period; and a third register which stores a third value SYSTIME2 which is input from the first counter at the end of a calibration period. Wake up time is determined using a relative frequency which is calculated from values stored in the above registers.

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First Claim