Addressing system in a multi-port RAM having main and cache memories
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United States of America Patent
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Jul 11, 2000
Grant Date -
N/A
app pub date -
Feb 4, 1998
filing date -
Mar 7, 1997
priority date (Note) -
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Abstract
A multi-port memory chip having a DRAM main memory and a SRAM cache memory coupled via a global bus. An addressing system enables the user to perform data transfers between external data ports and the SRAM concurrently with data transfers between the DRAM and the SRAM. To support DRAM operations, DRAM address pins on the memory chip select a data block in the DRAM, and indicates a SRAM line for receiving or transferring data. To support SRAM operations, SRAM address pins determine addressed line and word in the SRAM. To reduce the number of pins on the memory chip the DRAM address pins and SRAM address pins are used for supplying commands that define various memory operations.
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