Read/write timing for maximum utilization of bidirectional read/write bus
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United States of America Patent
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Jul 11, 2000
Grant Date -
N/A
app pub date -
Sep 19, 1997
filing date -
Sep 20, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus for optimizing the efficiency of a data bus for a memory device. Extra latency is added between the time a memory controller issues a write instruction and the time the data is transferred on the data bus. This additional latency is optimized to reduce the number of idle time slots on the data bus when switching between a read instruction and a write instruction. Programmable registers are provided for adjusting the amount of latency.
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