Processor with multiple execution units and local and global register bypasses
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Jul 11, 2000
Grant Date -
N/A
app pub date -
Mar 30, 1999
filing date -
Mar 30, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
A method and an apparatus for data processing between multiple execution units using local and global register bypasses is disclosed. In one embodiment, the device contains a register file, at least two bypass circuits, a plurality of execution units, and a control circuit. Each bypass circuit connects to at least one execution unit. The control circuit, which is coupled to the execution units, limits no more than one clock delay per each execution clock cycle. The control circuit further designates delay clock cycles for handling delays.
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