Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer
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United States of America Patent
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-
Jul 18, 2000
Issued Date -
N/A
app pub date -
Oct 2, 1998
filing date -
Nov 14, 1996
priority date (Note) -
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Abstract
A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
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