Interleaved zero current switching in a power factor correction boost converter
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United States of America Patent
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Jul 18, 2000
Grant Date -
N/A
app pub date -
Jan 14, 1999
filing date -
Jan 14, 1999
priority date (Note) -
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Abstract
A method and apparatus for interleaving switching of multiple transistor switches in a power factor correction (PFC) boost converter and for timing the switching to occur when a current through a freewheeling diode corresponding to each switch is at a minimum level. The converter draws input current from an alternating current power supply for forming a regulated output voltage. A controller senses an input current and an output voltage across an output capacitor for controlling switching to regulate the output voltage and to ensure that the input current is substantially in phase with an input voltage. Current through a first inductor associated with a first switch is allowed to fall substantially to zero upon discharging the first inductor prior to re-charging the first inductor. Charging of a second inductor associated with a second switch, however, is initiated prior to completion of discharging the first inductor. Similarly, current through the second inductor is allowed to fall substantially to zero prior to re-charging the second inductor. An advantage is that from the perspective of the power supply, the converter operates in continuous conduction mode, while from the perspective of each of the switches, the converter operates in discontinuous conduction mode. The invention reduces power dissipated in the switches, increasing reliability and allowing higher frequency operation. In accordance with another aspect of the invention, a synchronizing signal is generated by the PFC converter for synchronizing operation of a second converter, such as a pulse-width modulation converter, with the PFC converter.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| FAIRCHILD SEMICONDUCTOR CORPORATION | 82 RUNNING HILL ROAD SOUTH PORTLAND ME 04106 |
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- [Patents Count]
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Hwang, Jeffrey | Saratoga, CA | 30 | 546 |
| Li, Thomas | Mountain View, CA | 44 | 639 |
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| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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