Importance

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Abstract

A system which performs chained direct memory access (DMA) operations, includes a working set of buffers, a first-in-first-out memory, a first DMA co-processor, a second DMA co-processor and a controlling processor. The working set of buffers are available for receiving data from chained DMA operations. The first-in-first-out memory store addresses of buffers, from the working set of buffers, which are available for immediate allocation. The first DMA co-processor and the second DMA co-processor perform the chained DMA operations. The controlling processor sets up the chained DMA operations and adds addresses of free buffers to the first-in-first-out memory. When performing a first chained DMA operation, the first DMA co-processor accesses the first-in-first-out memory to allocate for itself a first buffer from the queue of buffers when a first link in the first chained DMA operation requires a buffer. When the first buffer is filled, the first DMA co-processor immediately notifies the controlling processor. When performing a second chained DMA operation, the second DMA co-processor accesses the first-in-first-out memory to allocate for itself a second buffer from the queue of buffers when a first link in the second chained DMA operation requires a buffer. When the second buffer is filled, the second DMA co-processor immediately notifies the controlling processor.

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First Claim