Microfabrication process for enclosed microstructures
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United States of America Patent
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Jul 25, 2000
Grant Date -
N/A
app pub date -
Jun 2, 1997
filing date -
Jun 2, 1997
priority date (Note) -
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Abstract
A single-mask process for fabricating enclosed, micron-scale subsurface cavities in a single crystal silicon substrate includes the steps of patterning the substrate to form vias, etching the cavities through the vias, and sealing the vias. Single cavities of any configuration may be produced, but a preferred embodiment includes closely spaced cavity pairs. The cavities may be separated by a thin membrane, or may be merged to form an enlarged merged cavity having an overhanging bar to which electrical leads may be connected. A three-mask process for fabricating enclosed cavities with electrical contacts and electrical connections is also disclosed.
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