Integrated circuitry and semiconductor processing method of forming field effect transistors

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United States of America Patent

PATENT NO 6093661
SERIAL NO

09386076

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms. Transistor gates are formed over the first and second gate dielectric layers, and then p-type source/drain regions are formed proximate the transistor gates in the first area and n-type source/drain regions are formed proximate the transistor gates in the second area.

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Patent Owner(s)

  • MICRON TECHNOLOGY, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Trivedi, Jigish D Boise, ID 107 1311
Wang, Zhongze Boise, ID 153 1504
Yang, Rongsheng Boise, ID 30 497

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