High speed common mode logic circuit
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United States of America Patent
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-
Jul 25, 2000
Grant Date -
N/A
app pub date -
Jul 16, 1998
filing date -
Jul 16, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A common mode logic (CML) circuit having an improved bias circuit and an active MOS load operating exclusively in the triode region to provide improved performance characteristics including a high speed of operation. The bias circuit of the CML circuit comprises a pair of MOS transistors, one of which has an aspect ratio (W.sub.P /L.sub.P) and the other of which has an aspect ratio (W.sub.P /L.sub.P)/n, wherein 1
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