Digital signal processor using a reconfigurable array of macrocells
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 25, 2000
Grant Date -
N/A
app pub date -
Feb 5, 1998
filing date -
Feb 5, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A real time digital systolic processor with a core of reconfigurable interconnected macrocells which can be programmed according to function for processing high bandwidth digital data. Each macrocell contains arithmetic logic units for performing predetermined functions based on format of the input data stream from an outside source or from other macrocells. The interconnects between each macrocell are arranged so that the function of the device is predetermined according to user specific applications.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully