Importance

Loading Importance Indicators...

Abstract

An architecture for data correction that may be used in non-volatile random access memories. In one embodiment, a circuit configured to be responsive to a control signal and to provide bitline outputs in response to bitline inputs is provided. The states of the bitline outputs depend upon the states of the bitline inputs and the control signal. The control signal may be provided by a non-volatile static random access memory (SRAM) cell. The circuit may include inverting and non-inverting paths or may include crossing and passing circuitry. The crossing and passing circuitry connects a first input of the circuit to a second output of the circuit in response to a first state of the control signal and further connects the first input to a first output of the circuit in response to a second state of the control signal. The control signal may be generated by a control device such as a non-volatile random access memory cell. In other embodiments, the circuit is configured to select a first bit-line connection path or a second bit-line path according to the state of the control signal. If the control signal is in an active state, the first bit-line connection path is selected and if the control signal is in an inactive state, the second bit-line connection path is selected.

Loading the Abstract Image...

First Claim