Multi-modulus frequency divider
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United States of America Patent
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Aug 1, 2000
Grant Date -
N/A
app pub date -
Jul 17, 1998
filing date -
Jul 17, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A multi-ratio frequency divider, which is implemented in a BiCMOS (bipolar-complementary metal oxide semiconductor) circuit, includes a dual-modulus counter for dividing by P+1 and P. P+1 is a power of two and there is not necessary an additional flip-flop responsive to high input frequency, which consumes power due to bipolar transistor devices. An output from the counter is further divided by a variably set value. When its count reaches another set value, the division ratio of the dual-modulus counter is switched to another division ratio. When the further divided counter reaches the variably set value, a new cycle starts. The total division ratio of the multi-modulus frequency divider is a combination of the variably set division values, both being binary bit data. No decoder is necessary for converting an input division ratio to the set values.
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