Apparatus and method for address translation and allocation for a plurality of input/output (I/O) buses to a system bus
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United States of America Patent
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-
Aug 1, 2000
Issued Date -
N/A
app pub date -
Apr 6, 1995
filing date -
Oct 22, 1992
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Multiple subsystem I/O (Input/Output) buses are coupled to one or more system buses of a computer system by interface circuits which perform necessary decoding of memory space and I/O (Input/Output) space for allocation of portions of the memory space and the I/O (Input/Output) space to each I/O (Input/Output) bus. The interface circuits also translate fixed addresses within each I/O (Input/Output) bus to permit proper operation of the I/O (Input/Output) buses with the computer system. The interface circuits are programmed by the computer system to define the allocated memory spaces and I/O (Input/Output) spaces for the corresponding I/O (Input/Output) buses. Programming of the I/O (Input/Output) buses is performed at the time of system configuration by writing appropriate values into configuration registers incorporated into each of the interface circuits.
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