Multiple bus system using a data transfer unit
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United States of America Patent
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-
Aug 1, 2000
Grant Date -
N/A
app pub date -
Aug 17, 1999
filing date -
Jun 4, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controlling connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
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