Fault tolerant computer system
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United States of America Patent
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Aug 1, 2000
Issued Date -
N/A
app pub date -
Jun 25, 1997
filing date -
Jun 5, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A computer system includes an apparatus which enables transactions directed to a particular target device such as one situated inside a bridge to be shunted directly to the device without requiring that the transaction actually proceed to the device through a bus on which the device is located. However, the transaction may, in fact, also be run on the bus on which the device is located, the ID select for the target device may be masked. In this way, it is possible to run transactions to a particularly critical device even when the bus on which it is located is, for one reason or another, not operating.
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