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Abstract

An efficient memory retrieval/storage schemes for a fault tolerant memory control system for a computer system having a host processor, a mass storage memory and a system interconnect. The memory control system includes a primary memory controller and a backup memory controller with taps between the memory controllers to increase fault tolerance. Data is transferred between the host processor and the mass storage memory in the form of data packets. During a write operation, instead of receiving a data packet from the host processor, storing the data content, retrieving the data and then generating a new data packet for the mass storage memory, the memory controller redirects the data packets without the need to copy the data into the controller cache. Similarly, during a read operation, instead of receiving a data packet from the mass storage memory, storing the data content, retrieving the data and then generating a new data packet for the host processor, the memory controller redirects the data packets without the need to copy the data into the controller cache. Upon receipt of the data packets, verification packets are sent from the memories devices to the memory controller which then sends a confirmation packet to the host processor. Advantages of the present invention include reduced load on the system interconnect, reduced latency in backing up data, and reduced latency in recovering from partial system failures. In addition, the change in software and hardware needed to implementation such a solution is minimal since most of the backup functionality is provided by existing hardware.

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First Claim