Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line
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United States of America Patent
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Aug 8, 2000
Grant Date -
N/A
app pub date -
Aug 14, 1998
filing date -
Aug 14, 1998
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Abstract
Conductive structures, conductive lines, conductive SRAM lines, integrated circuitry, SRAM cells, and methods of forming the same are described. In one embodiment, a substrate is provided and a layer comprising TiN is physical vapor deposited over the substrate having greater than or equal to about 90% by volume <200> grain orientation. In another embodiment, at least two components are electrically connected by forming a layer of TiN over a substrate having the desired by-volume concentration of <200> grain orientation, and etching the layer to form a conductive line. In a preferred embodiment, conductive lines formed in accordance with the invention electrically connect at least two SRAM components and preferably form cross-coupling electrical interconnections between first and second inverters of an SRAM cell.
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