Semiconductor device and method of manufacturing the same
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United States of America Patent
Stats
-
Aug 8, 2000
Grant Date -
N/A
app pub date -
Dec 30, 1998
filing date -
Jan 14, 1998
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A first semiconductor chip is produced by affixing a thermo-compression sheet to the back surface of a wafer having a circuit formed on its front surface. The first semiconductor chip is mounted on a circuit board including an insulating substrate and a wiring layer provided on the insulating substrate so that the back surface of the first semiconductor chip faces the circuit board. A second semiconductor chip produced in the same manner as the first semiconductor chip is mounted on the first semiconductor chip with its back surface facing the first semiconductor chip. Each of the first and second semiconductor chips is wire-bonded to the wiring layer with a wire. The first and second semiconductor chips and the wire are sealed with a sealing resin. The wiring layer is connected to external connection terminals through via holes provided in the insulating substrate.
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- 15 United States
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- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| KATANA SILICON TECHNOLOGIES LLC | 8105 RASOR BOULEVARD SUITE 210 PLANO TX 75024 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Fukui, Yasuki | Tenri, JP | 17 | 569 |
| Matsune, Yuji | Tenri, JP | 4 | 301 |
| Narai, Atsuya | Yamatokoriyama, JP | 8 | 418 |
| Sota, Yoshiki | Nara, JP | 33 | 1258 |
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| Fee | Large entity fee | small entity fee | micro entity fee |
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| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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