Importance

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Abstract

A system and method for decoding fixed length data words comprising variable length objects is disclosed having the ability to decode a variable length DCT in every clock cycle. The system includes multiple floating point registers, preferably two, for holding the fixed length data words, and a tracking arrangement, including a summation block and a total used bits register, where the summation block sums bits used for each variable length object with the contents of the total bits used register to form the total number of used bits. The total used bits are fed back and summed within the total used bits register. The system also has a rotating shift register, which is a circular buffer, and a multiplexer arrangement which transfers variable length objects from the floating point registers to the rotating shift register. The tracking arrangement counts the bits used in transferring variable length objects to the rotating shift register. The floating point registers access additional fixed length data words when emptied. The multiplexer arrangement includes one multiplexer is associated with each floating point register and is capable of receiving new data. Each multiplexer transfers data from its associated floating point register to the rotating shift register. The transfer of variable length objects may require data contained in more than one floating point register and transfer using more than one multiplexer. The system also includes a resultant floating point register, where the rotating shift register shifts complete data words data thereto.

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First Claim