Methods for debugging a multiprocessor system
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United States of America Patent
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Aug 8, 2000
Grant Date -
N/A
app pub date -
Nov 14, 1997
filing date -
Nov 14, 1997
priority date (Note) -
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Abstract
A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.
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