Importance

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Abstract

One embodiment of the present invention provides an apparatus for aligning a data signal and a data clock signal received from a memory during a read operation. The apparatus includes a data input for receiving the data signal, and a clock input for receiving the data clock signal. The data signal and the data clock signal feed into an offset mechanism that determines an offset between the data clock signal and the data signal. This offset feeds into a comparison mechanism that determines if the offset is outside of a valid range. If the offset is outside of the valid range, an adjustment mechanism adjusts a delay between the data clock signal and the data signal. In a variation on the above embodiment, the apparatus is implemented in special-purpose hardware within a memory controller, and operates periodically while the computer system is running. In another variation, the apparatus is implemented as part of a system BIOS program stored in read only memory and operates during system startup.

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First Claim