Semiconductor device including a wire pattern for relaying connection between a semiconductor chip and leads
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United States of America Patent
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Aug 15, 2000
Grant Date -
N/A
app pub date -
Apr 16, 1998
filing date -
Apr 17, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
An insulation material and a wire pattern are provided on at least one of the surfaces of a die pad. Wires of the wire pattern are patterned in such a manner that at least one inner lead included in at least one of two lead groups is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the lead group including the above particular inner lead, while at least one inner lead included in the other lead group is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the other lead group. Accordingly, a multichip-1-package semiconductor device using any kind of semiconductor chip can be realized. Also, the costs of the semiconductor device are saved and the semiconductor device can be developed in a shorter period by omitting the design modification of the semiconductor chip.
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