System and method for edge termination of parallel conductive planes in an electrical interconnecting apparatus

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United States of America Patent

PATENT NO 6104258
SERIAL NO

09081372

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Abstract

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A system and method are presented for stabilizing the electrical impedance of an electrical interconnecting apparatus including a pair of parallel planar conductors separated by a dielectric layer. The electrical interconnecting apparatus may be, for example, a PCB, a component of a semiconductor device package, or formed upon a surface of an integrated circuit substrate. The present method includes determining a characteristic impedance of the structure. An electrical resistance is electrically coupled between regions of the planar conductors near peripheries, wherein the electrical resistance has a value dependent upon the characteristic impedance of the structure. The electrical resistance may be a set of discrete electrical resistances (e.g., resistors) dispersed about regions near peripheries of the planar conductors, or a continuous 'stripe' of electrical resistance between the regions. The electrical resistance serves to stabilize the electrical impedance of the pair of parallel planar conductors, thereby reducing an amount of electromagnetic energy radiated from the structure.

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Patent Owner(s)

Patent OwnerAddress
ORACLE AMERICA INC500 ORACLE PARKWAY REDWOOD SHORES CA 94065

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Novak, Istvan Sudbury, MA 30 424

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