Importance

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Abstract

A balanced switching circuit comprises a plurality of transfer gates, each transfer gate having an input terminal, an output terminal, and at least one control terminal adapted to receive a control signal. Each transfer gate, which may be comprised of pass transistors such as n- and p-channel metal oxide semiconductor (MOS) transistors, is operable to couple the input terminal to the output terminal in response to the control signal. The plurality of transfer gates are arranged in N rows and N columns with the input and output terminals of the N transfer gates in each row connected in series between a first signal terminal and a second signal terminal. Each transfer gate has its control terminal connected to one of N clock terminals adapted to receive respective clock signals. Each clock terminal is coupled to the control terminal of only one transfer gate in each row and only one transfer gate in each column. The balanced transfer gate circuit is operable to couple the first signal terminal to the second signal terminal in response to the clock signals. The transfer gates are selectively clocked or activated such that the switching speed is independent of the order in which the individual series connected past transistors or transfer gates are activated. A shift register circuit, a memory device, and a computer system utilizing such a balanced switching circuit are also described.

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First Claim