Compliant wirebond packages having wire loop
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United States of America Patent
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-
Aug 22, 2000
Issued Date -
N/A
app pub date -
Sep 1, 1999
filing date -
Dec 13, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A semiconductor chip assembly with a frame having an aperture, a continuous rail enclosing the aperture and bonds pads disposed on the top surface of the continuous rail; a semiconductor chip having contacts on its top surface fitted within the aperture; a plurality of wire loops connecting the bond pads to the contacts, and a compliant layer disposed over the first surface of the semiconductor chip and the plurality of wire loops such that the top portion of each wire loop is exposed. The semiconductor chip assembly can be incorporated into a larger assembly by connecting the wire loops to connection pads on an external substrate.
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