Interconnect structure for FPGA with configurable delay locked loop
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United States of America Patent
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-
Aug 22, 2000
Grant Date -
N/A
app pub date -
Aug 19, 1998
filing date -
Aug 19, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
A field programmable gate array (FPGA) is provided that includes a plurality of pads and a plurality of delay locked loops (DLLs). Programmable connections enable any one of the DLLs to have multiple pads as inputs. Programmable connections also enable the DLLs to be selectively connected to one another. Programmable connections further enable the pads to be selectively connected to general interconnect circuitry or global clock drivers of the FPGA. Programmable connections are also provided for selectively connecting the DLLs to the global clock drivers. This FPGA structure enables the pads to be configured to receive either clock or non-clock signals. This structure also enables the FPGA to operate as a clock mirror, and to generate one clock signal from another clock signal on the FPGA.
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