Layout design method and system for an improved place and route
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Aug 29, 2000
Grant Date -
N/A
app pub date -
May 13, 1998
filing date -
May 13, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A layout design method and system for a semiconductor integrated circuit improves circuit performances related to operated frequency and power consumption by improved placement and routing. The method features an intersecting wiring predicting step that predicts the number of the intersecting wirings based on predicted wiring routes and an intersecting wiring capacitance calculating step that calculates the capacitances between the intersecting wirings.
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