Multi-cycle I/O ASIC communication system having an arbiter circuit capable of updating address table associated with each I/O ASIC on bus
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United States of America Patent
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-
Aug 29, 2000
Grant Date -
N/A
app pub date -
Mar 19, 1998
filing date -
Mar 19, 1998
priority date (Note) -
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Abstract
An arbiter circuit is employed to isolate a processor from a plurality of Input/Output Application Specific Integrated Circuits ('I/O ASICs'). The processor is coupled to the arbiter through a control bus, an address bus and a data bus. The arbiter is coupled to the I/O ASICs through an extension of the control bus and a combined address/data bus. The arbiter manages control of the control bus extension and address/data bus to enable contemporaneous transmission ('broadcast') of messages to the I/O ASICs, and enable the processor to access the I/O ASICs. Only one of the I/O ASICs is granted control of the control bus extension and address/data bus at any point in time. The processor may also be granted sole control of the control bus extension and address/data bus.
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