Via patterning for poly(arylene ether) used as an inter-metal dielectric

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United States of America Patent

PATENT NO 6114253
SERIAL NO

09268542

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Abstract

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A process for removal of residual silicon oxide hardmask used to etch vias in low-k organic polymer dielectric layers is described. The hardmask deteriorates by developing an angular aspect or faceting along the pattern edges when used to etch organic polymer layers in an oxygen/inert gas plasma in a high density plasma etcher. In addition the deterioration of the hardmask during organic polymer etching causes a significant degradation of surface planarity which would result in via-to-via shorts when a second metal layer is patterned over it if the hardmask were left in place. The residual hardmask is selectively removed immediately after the via etch by a soft plasma etch which restores surface planarity and removes via edge facets. The plasma etch has a high selectivity of oxide-to-organic polymer so that the surface irregularities are not transferred to the polymer surface and the exposed metal surface at the base of the via is also unscathed.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Huang, Ming-Hsin Hsin-Chu, TW 18 217
Jang, Syun-Ming Hsin-Chu, TW 374 6646
Yu, Chen-Hua Hsin-Chu, TW 2039 41095

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