Integrated circuit memory cell having a small active area and method of forming same
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United States of America Patent
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Sep 5, 2000
Issued Date -
N/A
app pub date -
May 27, 1999
filing date -
Jan 28, 1997
priority date (Note) -
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Abstract
A method for manufacturing a memory device having a plurality of memory cells. Each memory cell has a non-volatile resistive memory element with a small active area. A plurality of memory cells are formed at selected locations of at least a portion of a semiconductor wafer. To form the memory cells, a lower electrode layer and a memory material layer are deposited over at least a portion of the wafer. Patterns are formed over desired contact locations of the memory material layer and etching is used to remove portions of the memory material layer. The etching step undercuts the patterns and forms memory elements having a protruding contact portion with an apex contact area. The pattern is removed, and an upper electrode is formed and electrically coupled to the contact area. Corresponding access devices and word/bit line conductor grids are provided and coupled to the memory cells.
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