Semiconductor package with translator for connection to an external substrate
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Sep 5, 2000
Grant Date -
N/A
app pub date -
May 29, 1998
filing date -
May 30, 1997
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An electronic assembly which includes a semiconductor chip package having an array of package terminals and a translator. The translator has a first array of terminals exposed on a first surface of the translator and a second array of terminals exposed on a second surface of the translator. The pitch of the first array matches the pitch of the semiconductor package. The pitch of the second array matches the pitch of the printed circuit board to which the electronic assembly is to be mounted. The array of package terminals on the semiconductor chip package is aligned with and bonded to the first array of terminals on the translator to form the electronic assembly. The electronic assembly can then be mounted on a board by aligning and bonding the second array of terminals on the translator with the connection pads on the printed circuit board.
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