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Abstract

The object of the invention is to provide a lock-in process and device for a YIG-tuned oscillator which takes into account ageing and hysteresis of the YIG-tuned oscillator. This object is attained in that during a predetermined frequency change, the frequency of the YIG-tuned oscillator (1) is preset by means of a microprocessor (17) that progressively changes the current (I.sub.SP) in the main tuning coil (13) of the YIG-tuned oscillator (1) by an iterative capture routine, until the capture range (.DELTA.FM) of the switched-on frequency-locked loop, which changes with the coil current (I.sub.SP), includes the new operating frequency (f.sub.SET). The switched-on frequency-locked loop then pulls the oscillator frequency into the capture range of the PLL and the PLL locks-in the oscillator frequency to the new operating frequency (f.sub.SET). The microprocessor (17) interrupts the capture routine when a PLL-LOCK detector (11) announces to the microprocessor (17) that the new operating frequency (f.sub.SET) has been successfully locked-in. The invention is used in a process for locking-in a phase-locked loop (PLL) to a YIG-tuned oscillator whose frequency is brought into the PLL capture range by a frequency-locked loop equipped with a frequency discriminator. When the PLL is locked-in, the frequency-locked loop can be switched off.

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First Claim