Semiconductor memory device using MONOS type nonvolatile memory cell

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United States of America Patent

PATENT NO 6118699
SERIAL NO

09352838

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Abstract

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That surface portion of a semiconductor substrate which is adjacent to a buried source region formed in the substrate is covered with an offset side wall to suppress expansion of a channel beneath the offset side wall. In addition, buried source regions in the form of offset side walls are formed on the two sides of a drain region having one non-offset side wall to prevent a write or read error in unselected memory cell transistors on both sides of a selected memory transistor either in a data write or in a data read.

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Patent Owner(s)

Patent OwnerAddress
KABUSHIKI KAISHA TOSHIBAMINATO-KU TOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Minagawa, Hidenobu Kawasaki, JP 10 207
Ohta, Hitoshi Yokohama, JP 51 756
Satou, Kazuhiko Yokohama, JP 28 233
Suzuki, Noriaki Yokohama, JP 63 375
Tatsumi, Yuuichi Tokyo, JP 19 260

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