Method of operating a field programmable memory array with a field programmable gate array
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United States of America Patent
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Sep 12, 2000
Grant Date -
N/A
app pub date -
Nov 10, 1998
filing date -
Dec 20, 1995
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Abstract
A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
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