Memory controller architecture
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United States of America Patent
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Sep 12, 2000
Grant Date -
N/A
app pub date -
Feb 18, 1998
filing date -
Apr 30, 1997
priority date (Note) -
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Abstract
An apparatus for providing a number of ports with burst access to a DRAM array includes a memory array, a controller for controlling the memory array, a write device for writing to the memory array, a read device for reading from the memory array, a FIFO output buffer for temporarily storing data read from the memory array and/or a FIFO input buffer for temporarily storing data prior to writing to the memory array.
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