I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
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United States of America Patent
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Sep 12, 2000
Issued Date -
N/A
app pub date -
Oct 8, 1997
filing date -
Dec 20, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A uniform bus system is provided which operates without any special consideration by a programmer. Memories and peripheral may be connected to this bus system without any special measures. Likewise, units may be cascaded with the help of the bus system. The bus system combines a number of internal lines, and leads them as a bundle to terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system.
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