Mechanism for sharing data cache resources between data prefetch operations and normal load/store operations in a data processing system
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United States of America Patent
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Sep 12, 2000
Grant Date -
N/A
app pub date -
Aug 3, 1998
filing date -
Aug 3, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A data processing system (10) provides a mechanism for choosing when the data stream touch (DST) controller (300) is allowed access to the data cache and MMU (50). The mechanism uses a count value to determine at what point in program execution the DST controller (300) is allowed to interrupt normal load and store accesses. This allows DST prefetches to be optimized for maximum performance of the data processing system (10).
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