Synchronization and control system for an arrayed processing engine
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United States of America Patent
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Sep 12, 2000
Grant Date -
N/A
app pub date -
Jun 29, 1998
filing date -
Jun 29, 1998
priority date (Note) -
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Abstract
A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control system further includes an input header buffer (IHB) and an output header buffer (OHB), the latter comprising circuitry for receiving current transient data processed by the pipelines and for decoding control signals to determine a destination for the processed data. One destination is a feedback path that couples the OHB to the IHB and returns the processed data to the IHB for immediate loading into an available pipeline.
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