Reduced size integrated circuits and methods using test pads located in scribe regions of integrated circuits wafers
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United States of America Patent
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Sep 19, 2000
Grant Date -
N/A
app pub date -
Nov 30, 1998
filing date -
Dec 31, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Integrated circuit regions are formed on an integrated circuit wafer. The integrated circuit wafer includes scribe regions located between the integrated circuit regions, the scribe regions include test pads that are electrically connected to the test circuits of integrated circuit regions via conductive lines. Test functions are provided to the test circuits in the integrated circuit regions via the test pads to determine the operability of the integrated circuit regions. The integrated circuit regions are separated from the plurality of scribe regions and the plurality of test pads located therein. Separating the integrated circuit regions from the scribe regions and the test pads, thereby may allow a reduction in the number of pads in the integrated circuits and a corresponding decrease in the size of respective integrated circuit packages.
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